As semiconductor technology has advanced, the amount and speed of logic available on an IC, such as a field programmable gate array (FPGA), has increased more rapidly than the number and performance of I/O connections. As a result, IC die stacking techniques have received renewed interest to address the interconnection bottleneck of high-performance systems (also referred to as three-dimensional (3D) ICs). In 3D IC applications, two or more IC devices and/or substrates are stacked vertically and interconnections are made between them. Exemplary stacked arrangements include a mother IC and one or more daughter ICs stacked thereon, such as an FPGA mother IC with one or more memory daughter ICs; or a plurality of ICs stacked on an interposing substrate, such multiple FPGAs and/or other ICs (e.g., RAM) mounted side-by-side on an interposing substrate.
In stacked arrangements, ICs are typically mounted to other ICs/substrates using relatively small solder bumps (“micro-bumps”). Such micro-bumps are small relative to the conventional C4 bumps using in IC packaging. Through substrate vias (TSVs) (also referred to as through die vias (TDVs)) can be employed to establish interconnections between stacked ICs/substrates. A TSV is a metal via that extends through a substrate for coupling to another substrate that is vertically stacked on the substrate. Further, stacked IC/substrate arrangements can be packaged in a single package having a plurality of C4 bumps or like type IC terminals.
In conventional flip-chip packages, C4 bumps that encounter the highest thermal and/or mechanical stress (“thermo-mechanical stress”) are well known. Such high-stress bumps are typically located in the corner and/or edge of the IC substrate. Thermo-mechanical finite element modeling (FEM) of chip-package corners and edges can be used to provide a package-level stress analysis. Such modeling can take a day to many days to complete using present-day computers and workstations. In a 3D IC with many micro-bumps and TSVs, thermo-mechanical stress depends on many factors, including die location, location of micro-bumps with respect to TSVs, local temperature, back end of line (BEOL) metallization and dielectric configuration, material composition, die/interposer thickness, and the like. Also, the number of micro-bumps in a typical 3D IC is 10 to 1000 times higher than the number of C4 bumps in a conventional flip-chip package. Thus, thermo-mechanical modeling of a 3D IC using conventional processes can be impractical in terms of the time to perform such modeling, particularly given the complexity of 3D ICs compared to conventional IC packages.
Accordingly, there exists a need in the art for a method and apparatus for integrated circuit package thermo-mechanical reliability analysis that overcomes the aforementioned disadvantages.